PIC16C63A-04I/SO【PDF 78/184 页】IC MCU OTP 4KX14 PWM 28SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3841

74页 75页 76页 77页 [78页]79页 80页 81页 82页

169

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link

at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.

The ARM core enters Interrupt mode, if it has not already done so.

When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value

read in AIC_IVR. Reading the AIC_IVR has the following effects:

– Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current

level is the priority level of the current interrupt.

– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in

order to de-assert nIRQ.

– Automatically clears the interrupt, if it has been programmed to be edge-triggered.

– Pushes the current level and the current interrupt number on to the stack.

– Returns the value written in the AIC_SVR corresponding to the current interrupt.

The previous step has the effect of branching to the corresponding interrupt service routine. This should

start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four

when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For

example, the instruction SUB PC, LR, #4 may be used.

Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ

to be taken into account by the core. This can happen if an interrupt with a higher priority than the current

interrupt occurs.

The interrupt handler can then proceed as required, saving the registers that will be used and restoring

them at the end. During this phase, an interrupt of higher priority than the current level will restart the

sequence from step 1.

Note:

If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.

The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is

completed in an orderly manner.

The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that

the current interrupt is finished. This causes the current level to be popped from the stack, restoring the

previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority

than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted,

but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is

restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of

returning from the interrupt to whatever was being executed before, and of loading the CPSR with the

stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.

Note:

The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt

when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (inter-

rupt is masked).

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式